Silicon Labs /EFM32PG23B210F512IM48 /EUSART2_NS /FRAMECFG

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Interpret as FRAMECFG

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DATABITS 0 (NONE)PARITY 0 (HALF)STOPBITS

STOPBITS=HALF, PARITY=NONE

Description

No Description

Fields

DATABITS

Data-Bit Mode

1 (SEVEN): Each frame contains 7 data bits

2 (EIGHT): Each frame contains 8 data bits

3 (NINE): Each frame contains 9 data bits

4 (TEN): Each frame contains 10 data bits

5 (ELEVEN): Each frame contains 11 data bits

6 (TWELVE): Each frame contains 12 data bits

7 (THIRTEEN): Each frame contains 13 data bits

8 (FOURTEEN): Each frame contains 14 data bits

9 (FIFTEEN): Each frame contains 15 data bits

10 (SIXTEEN): Each frame contains 16 data bits

PARITY

Parity-Bit Mode

0 (NONE): Parity bits are not used

2 (EVEN): Even parity are used. Parity bits are automatically generated and checked by hardware.

3 (ODD): Odd parity is used. Parity bits are automatically generated and checked by hardware.

STOPBITS

Stop-Bit Mode

0 (HALF): The transmitter generates a half stop bit. Stop-bits are not verified by receiver

1 (ONE): One stop bit is generated and verified

2 (ONEANDAHALF): The transmitter generates one and a half stop bit. The receiver verifies the first stop bit

3 (TWO): The transmitter generates two stop bits. The receiver checks the first stop-bit only

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